The present invention relates to memory devices, and more particularly to a method and system for decreasing the spaces between word lines.
Flash memory devices are currently a popular form of storage. In certain flash memory devices, such as in NAND technology, an asymmetric pitch is desired. For example, FIGS. 1A and 1B depicts such a flash memory device 1. Referring to FIG. 1A, the flash memory device 1 includes gate stacks 10 and 20 on a substrate 2. The gate stacks 10 and 20 share a source 6 and each have a drain 4 and 8, respectively. A thin insulating layer 9 also covers the semiconductor substrate 2. The gate stack 10 includes a floating gate 12, an insulating layer 14 and a control gate 16. Similarly, the gate stack 20 includes a floating gate 22, an insulating layer 24 and a control gate 26. The insulating layers 14 and 24 typically include an ONO layer, which has two oxide layers separated by a nitride layer. The floating gates 12 and 22 and the control gates 14 and 24 are typically formed using first and second polysilicon layers, respectively.
Referring to FIG. 1B, a plan view of the flash memos device 1 is show. Lines 30 and 32 are formed from the first polysilicon layer. The lines 30 and 32 form the floating gates at intersections between the lines 40, 42 and 44 and the lines 30 and 32. Similarly, the word lines 40, 42 and 44 form the control gates at the intersections between the lines 40, 42 and 44 and the lines 30 and 32. Word lines 40, 42 and 44 are formed from a second polysilicon layer. Typically, the portions of the lines 30 and 32 are removed using a self-aligned etch after the word lines 40, 42 and 44 are formed. This allows the floating gates for different memory cells to be electrically insulated in the case where the lines 30 and 32 are made of semi-conductive material such as polysilicon. In the flash memory device 1 shown, the pitch of the word lines 40, 42 and 44 is asymmetric. In other words, the width of the word lines 40, 42 and 44 is different from the width of the spaces 50 and 52 between the word lines 40, 42 and 44. In general, the word lines 40, 42 and 44 are desired to be slightly wider than the spaces 50 and 52 between the word lines 40, 42 and 44. Typically, the gate stacks 10 and 20 are desired to be closely spaced. Similarly, the word lines 40, 42 and 44 are desired to be as close as possible. Furthermore, the word lines are desired to be slightly larger than the spaces between the word lines. Thus, the smallest feature is generally the spaces 50 and 52 between the word lines 40, 42 and 44.
FIG. 2 depicts a conventional method 60 for providing the conventional flash memory device 1 in which the pitch of lines, such as the word lines 40, 42 and 44, is asymmetric. A polysilicon layer from which the word lines will be formed is deposited, via step 62. The polysilicon layer typically covers the ONO layer 14 and 24 for the gate stacks 10 and 20. A layer of photoresist is provided, via step 64. The photoresist is then exposed to print the desired asymmetric pattern onto the photoresist, forming an asymmetric mask, via step 66. Apertures in the asymmetric mask expose portions of the polysilicon to be etched and thus correspond to spaces 50 and 52 between the polysilicon lines 40, 42 and 44. Areas which the asymmetric mask covers will become the polysilicon lines 40, 42 and 44. Thus, the asymmetric mask has an asymmetric pitch that matches the desired asymmetric pitch of the word lines 40, 42 and 44.
The polysilicon is then etched to transfer the pattern on the asymmetric mask to the polysilicon, via step 68. Thus, the portions of the polysilicon exposed by apertures in the asymmetric mask are removed in step 68. Thus, polysilicon lines, such as the word lines 40, 42, and 44, are formed in step 68. The asymmetric mask is then stripped, via step 70. A layer of insulator is then deposited on the polysilicon lines, via step 72. The insulator fills the spaces 50 and 52 between the polysilicon lines.
Using the method 60, word lines 40, 42 and 44 having an asymmetric pitch can be formed. The width of the word lines 40, 42 and 44 as well as the spaces 50 and 52 between the word lines 40, 42 and 44 are defined by the asymmetric mask formed in steps 64 and 66. Thus, as discussed above, the asymmetric mask has the same asymmetric pitch as the word lines 40, 42 and 44. In other words, the width of the apertures in the asymmetric mask matches the width of the spaces 50 and 52 between the word lines 40, 42 and 44. Similarly, the portions of the asymmetric mask which cover the polysilicon have the same width as the word lines 40, 42 and 44. Thus, transferring the pattern of the asymmetric mask to the polysilicon layer in step 68 results in word lines 40, 42 and 44 having the desired asymmetric pitch.
Because the word lines 40, 42 and 44 are desired to be wider than the spaces between the lines, the areas in the asymmetric mask which cover the polysilicon layer are wider than the apertures in the asymmetric mask. Thus, the smallest feature in the asymmetric mask are the apertures and the smallest feature on the flash memory device 1 are the spaces 50 and 52 between the word lines 40, 42 and 44.
Although the method 60 functions, one of ordinary skill in the art will realize that the word lines 40, 42 and 44 cannot be packed closely together. The pitch of the word lines 40, 42 and 44 is limited by the spaces 50 and 52. The spaces 50 and 52 are the smallest feature on the flash memory device 1. Thus, the spaces 50 and 52 correspond to the apertures in the asymmetric mask. The size of the apertures is limited by the smallest feature that can be reliably printed on the asymmetric mask in step 66 and transferred to the polysilicon layer in step 68. The smallest feature that can be reliably printed is also known as the minimum feature size and is determined by resolution limit of the manufacturing tooling. The resolution limit of the manufacturing tooling is determined by the lens, the photomask and the light source used in the manufacturing tooling. Using certain current conventional techniques and certain manufacturing tooling, the minimum feature size for the asymmetric mask is approximately 0.15 micron. Note, however, that for other manufacturing tooling, the resolution limit and, therefore, the minimum feature size may be a different value. For the current conventional techniques and manufacturing tooling, the minimum feature size for the spaces 50 and 52 is approximately 0.15 micron. Consequently, for the flash memory device 1 to have an asymmetric pitch, each of the word lines 40, 42 and 44 must have a larger width than the spaces 50 and 52 and, therefore, must be greater than 0.15 micron in width. At the same time, the word lines 40, 42 and 44 are desired to be packed together as closely as possible. However, the widths of the spaces 50 and 52 are limited by the minimum feature size possible for the asymmetric mask. Thus, the packing of the word lines 40, 42 and 44 is also limited by the minimum feature size that can be printed on the asymmetric mask, typically approximately 0.15 microns. Thus, the pitch of the word lines is limited by the minimum feature size for printing the asymmetric mask.
Accordingly, what is needed is a system and method for decreasing the space between word lines, allowing the word lines to be packed more closely together and thus have a decreased pitch. The present invention addresses such a need.
The present invention provides a method and system for providing a semiconductor device. The method and system comprise providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system comprise providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also comprise trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system comprise providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches. The reverse mask includes a plurality of apertures having a first width. Each of the plurality of trenches has a width. In this aspect, the method and system also comprise trimming a second portion of the insulating layers to increase the width of each of the plurality of trenches and providing a plurality of lines in the plurality of trenches.
According to the system and method disclosed herein, the present invention provides a semiconductor device in which the word lines can have an asymmetric pitch and in which the spaces between the word lines can be smaller than the resolution limit of the apparatus used to fabricate the semiconductor device. Therefore, word lines can be more closely spaced allowing for a higher density of memory cells in the semiconductor device.